1. Field of the Invention
The present invention relates to a power MOSFET package, and in particular relates to a wafer-level power MOSFET package.
2. Description of the Related Art
FIGS. 1A and 1B respectively show a cross-sectional view and a three-dimensional view of a conventional power MOSFET package 10. As shown in FIGS. 1A and 1B, a power MOSFET chip 12 is disposed on a conducting carrier 16 and packaged in a body 14. The power MOSFET chip 12 has a gate contact region and a source contact region (not shown). The power MOSFET package 10 includes a pin 18g electrically connected to the gate contact region and a pin 18s electrically connected to the source contact region. The pins 18g and 18s further extend through the body 14. The power MOSFET chip 12 includes a drain contact region (not shown). The drain contact region is electrically connected to a pin 18d extending through the body 14 through the conducting carrier 16 thereunder.
However, in the package mentioned above, the power MOSFET devices need to be packaged into bodies one by one. The pins also need to be formed one by one. A lot of time and effort are needed. In addition, the body and the pin occupy a lot of space, which makes the forming of a small sized package difficult. The requirement of a smaller and lighter electronic product can not be satisfied.